The present invention relates to non-volatile memory elements, and more particularly to circuits for reading non-volatile memory elements.
Many electronic systems include memory devices. The memory devices are often used to store critical information that is needed by the electronic system. In some instances it is necessary for the memory device to provide non-volatile storage. Non-volatile memories allow for information to be permanently or semi-permanently stored such that removing power from the memory does not destroy the stored information. Example non-volatile memory devices include Erasable Programmable Read Only Memory (EPROM) as well as others.
The trend in the electronics industry is to reduce overall power consumption in electronic systems. This trend is largely due to the proliferation of battery powered electronic systems. In an effort to preserve battery life, battery powered devices require their electronics to consume less power under operation. Because electronics are often disabled to conserve power, non-volatile memory devices are well suited to preserve any critical information required by the electronics.
To further preserve power, read circuits typically read the memory devices at power-up and then latch the data. However; reading the memory devices at power-up requires the read circuit to interact with support circuitry. One such support circuit is a sensing circuit that detects and retriggers the read circuit when the power drops to a low voltage. Another support circuit is a bias sensing circuit that detects when a correct bias voltage is established before initiating the read cycle. In addition, the bias sensing circuit may detect when the reading of the memory device is complete.
While these prior designs worked, the read circuits and accompanying support circuitry were quite complex and consumed a significant area on the die. In addition, even though the read circuit itself appeared to consume low power because it was only on during the read cycle, the support circuitry used significant current.
The present invention provides a static memory system having a read circuit that allows memory elements to be continually read. Because the read circuit continually reads the memory elements, the present invention minimizes the amount of support circuitry. Thus, the read circuit in accordance with the present invention consumes less die area and consumes less power than prior read circuit designs.
In one embodiment, the static memory system includes two memory elements, a write circuit, and a read circuit. The write circuit is configured to store a charge on one of the memory elements. The charge represents a data value for a respective bit. The read circuit is configured to continually detect the charge stored on the memory element and to continually translate the charge into a logic value indicative of the data value. The read circuit performs the continual detection and translation while the static memory system is powered on.
In one aspect of the invention, the read circuit includes a current steering circuit and a detection and translation circuit. The current steering circuit is configured to direct a flow of a current through the read circuit. The direction of the flow depends on which memory element is storing the charge. The detection and translation circuit is coupled to the current steering circuit and is configured to detect the current and translate the current into the logic value.
In another aspect of the invention, the detection and translation circuit includes a first current mirror, a second current mirror, and a third current mirror. The current mirrors are configured to output the logic value at a voltage level corresponding to a voltage at one of two rails. In a further refinement, the static memory system includes an inverter. The current mirrors and the inverter are configured in a manner to disallow feed through current through the inverter.
In yet another aspect of the invention, the current steering circuit includes a current source coupled to a differential pair. The differential pair may include the two memory elements or may include a first and a second transistor that have dimensions similar to the two memory elements.
In still another aspect of the invention, the static memory system further includes a first and a second cascode transistor. The first cascode transistor is coupled to the differential pair and the first current mirror. The second cascode transistor is coupled to the differential pair and the third current mirror. Both the first and second cascode transistors are biased at a substantially constant voltage and are configured to prevent an accidental write to their respective memory elements.
In another embodiment of the invention, the static memory system includes a first circuit and a second circuit. The first circuit continually steers a current through the memory system while the memory system is powered on. The second circuit continually detects the current and translates the current into a logic value representing a data value stored in the memory system while the memory system is powered on. In a further refinement, the first circuit includes a current-source transistor that has a gate biased at a first substantially constant voltage. The source of the current-source transistor is coupled to a power supply. The current-source transistor conducts a substantially constant current. The second circuit includes a first current mirror, a second current mirror, and a third current mirror. The current mirrors are configured to output the logic value at a voltage level corresponding to a voltage at one of two rails.
In one aspect of the invention, the circuit further includes an inverter. The inverter and the current mirrors are configured in a manner whereby feed through current does not flow through the inverter.
In yet another embodiment, the present invention provides an apparatus for reading memory systems. The apparatus includes a current steering means, a detection means, and a translation means. The current steering means continually directs a flow of a current through the memory system while the memory system is powered on. The detection means continually detects the current based on a charge that is stored on a memory element while the memory system is powered on. The translation means continually translates the current into a logic value indicative of a data value when the memory system is powered on.
In still another embodiment, the present invention provides a method for reading a memory device. The method includes generating a substantially constant current, directing the current to flow continually through a differential pair and at least three current mirrors. The direction of current flow is based upon which of the memory elements is storing a charge. The charge represents a data value. The method further includes detecting the current continually in the at least three current mirrors and continually translating the detected current into a logic value representing the data value.